EP20K60ERI208-1
Loadable PLD, 1.72ns, CMOS, PQFP208Manufacturer: Altera
Categories: Programmable Logic Devices
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Altera EP20K60ERI208-1 is a loadable PLD from the Altera EP20K60 series, featuring a propagation delay of 1.72 ns and CMOS technology. This device is housed in a 208-pin PQFP package (JESD-30 Code: S-PQFP-G208) with a terminal pitch of 0.500 mm. It offers 148 I/O lines and supports a maximum clock frequency of 2173 MHz. The operating temperature range is specified from -40 °C to 100 °C, with a nominal supply voltage of 2.5 V. This component is suitable for applications in industrial, telecommunications, and computing sectors.
Additional Information
Series: EP20K60RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 28.0000 |
| Width | 28.0000 |
| Technology | CMOS |
| Clock_Frequency_Max | 2173.00000 |
| JESD_30_Code | S-PQFP-G208 |
| Number_of_Dedicated_Inputs | 4 |
| Number_of_I_O_Lines | 148 |
| Number_of_Inputs | 140 |
| Number_of_Outputs | 140 |
| Number_of_Terminals | 208 |
| Operating_Temperature_Max | 100.0 |
| Operating_Temperature_Min | -40.0 |
| Organization | 4 DEDICATED INPUTS, 148 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | PLASTIC/EPOXY |
| Package_Code | HFQFP |
| Package_Equivalence_Code | QFP208,1.2SQ,20 |
| Package_Shape | Square |
| Package_Style | FLATPACK, HEAT SINK/SLUG, FINE PITCH |
| Programmable_Logic_Type | LOADABLE PLD |
| Propagation_Delay | 1.720 |
| Seated_Height_Max | 4.1000 |
| Supply_Voltage_Max | 2.62500 |
| Supply_Voltage_Min | 2.37500 |
| Supply_Voltage_Nom | 2.5 |
| Surface_Mount | Yes |
| Terminal_Form | Gull Wing |
| Terminal_Pitch | 0.500 |
| Terminal_Position | QUAD |
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