EP20K600EFC672-3X
Loadable PLD, 2.92ns, CMOS, PBGA672Manufacturer: Altera
Categories: Programmable Logic Devices
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Altera EP20K600EFC672-3X is a CMOS Loadable PLD featuring 500 I/O lines and 504 input pins, with a macrocell output function. This component operates within a temperature range of 0°C to 85°C and utilizes a supply voltage of 1.8V nominal, with a minimum of 1.71V and a maximum of 1.89V. Its propagation delay is rated at 2.92ns, supporting a maximum clock frequency of 160MHz. The device is housed in a 672-terminal, square PBGA package (JESD-30 Code: S-PBGA-B672) with a terminal pitch of 1.00mm, measuring 27.00mm in length and width, and a seated height of 3.50mm. This PLD is suitable for applications in the industrial and telecommunications sectors.
Additional Information
Series: EP20K600RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Width | 27.0000 |
| Technology | CMOS |
| Length | 27.0000 |
| Clock_Frequency_Max | 160.00000 |
| JESD_30_Code | S-PBGA-B672 |
| Number_of_Dedicated_Inputs | 0 |
| Number_of_I_O_Lines | 500 |
| Number_of_Inputs | 504 |
| Number_of_Outputs | 500 |
| Number_of_Terminals | 672 |
| Operating_Temperature_Max | 85.0 |
| Operating_Temperature_Min | 0.0 |
| Organization | 0 DEDICATED INPUTS, 500 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | PLASTIC/EPOXY |
| Package_Code | BGA |
| Package_Equivalence_Code | BGA672,26X26,40 |
| Package_Shape | Square |
| Package_Style | GRID ARRAY |
| Programmable_Logic_Type | LOADABLE PLD |
| Propagation_Delay | 2.920 |
| Seated_Height_Max | 3.5000 |
| Supply_Voltage_Max | 1.89000 |
| Supply_Voltage_Min | 1.71000 |
| Supply_Voltage_Nom | 1.8 |
| Surface_Mount | Yes |
| Terminal_Form | Ball |
| Terminal_Pitch | 1.000 |
| Terminal_Position | Bottom |
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