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Programmable Logic Devices

EP20K600EFC672-3X

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EP20K600EFC672-3X

Loadable PLD, 2.92ns, CMOS, PBGA672

Manufacturer: Altera

Categories: Programmable Logic Devices

Quality Control: Learn More

Altera EP20K600EFC672-3X is a CMOS Loadable PLD featuring 500 I/O lines and 504 input pins, with a macrocell output function. This component operates within a temperature range of 0°C to 85°C and utilizes a supply voltage of 1.8V nominal, with a minimum of 1.71V and a maximum of 1.89V. Its propagation delay is rated at 2.92ns, supporting a maximum clock frequency of 160MHz. The device is housed in a 672-terminal, square PBGA package (JESD-30 Code: S-PBGA-B672) with a terminal pitch of 1.00mm, measuring 27.00mm in length and width, and a seated height of 3.50mm. This PLD is suitable for applications in the industrial and telecommunications sectors.

Additional Information

Series: EP20K600RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:
Technical Details:
Width27.0000
TechnologyCMOS
Length27.0000
Clock_Frequency_Max160.00000
JESD_30_CodeS-PBGA-B672
Number_of_Dedicated_Inputs0
Number_of_I_O_Lines500
Number_of_Inputs504
Number_of_Outputs500
Number_of_Terminals672
Operating_Temperature_Max85.0
Operating_Temperature_Min0.0
Organization0 DEDICATED INPUTS, 500 I/O
Output_FunctionMACROCELL
Package_Body_MaterialPLASTIC/EPOXY
Package_CodeBGA
Package_Equivalence_CodeBGA672,26X26,40
Package_ShapeSquare
Package_StyleGRID ARRAY
Programmable_Logic_TypeLOADABLE PLD
Propagation_Delay2.920
Seated_Height_Max3.5000
Supply_Voltage_Max1.89000
Supply_Voltage_Min1.71000
Supply_Voltage_Nom1.8
Surface_MountYes
Terminal_FormBall
Terminal_Pitch1.000
Terminal_PositionBottom

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