EP20K400FI672-1
Loadable PLD, 2.5ns, CMOS, PBGA672Manufacturer: Altera
Categories: Programmable Logic Devices
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Altera's EP20K400FI672-1 is a MAX II CPLD featuring a loadable PLD architecture. This CMOS device operates with a nominal supply voltage of 2.5V, ranging from 2.375V to 2.625V. It offers 502 I/O lines and 4 dedicated inputs, with a total of 672 terminals. The propagation delay is rated at 2.5ns, supporting clock frequencies up to 5000.00000 MHz. This component is housed in a square, 26x26 mm PBGA672 package with a 1.000 mm terminal pitch. The operating temperature range is -40°C to 100°C. Applications include industrial control, communication infrastructure, and consumer electronics.
Additional Information
Series: EP20K400RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Width | 27.0000 |
| Technology | CMOS |
| Length | 27.0000 |
| Clock_Frequency_Max | 5000.00000 |
| JESD_30_Code | S-PBGA-B672 |
| Number_of_Dedicated_Inputs | 4 |
| Number_of_I_O_Lines | 502 |
| Number_of_Inputs | 496 |
| Number_of_Outputs | 496 |
| Number_of_Terminals | 672 |
| Operating_Temperature_Max | 100.0 |
| Operating_Temperature_Min | -40.0 |
| Organization | 4 DEDICATED INPUTS, 502 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | PLASTIC/EPOXY |
| Package_Code | BGA |
| Package_Equivalence_Code | BGA672,26X26,40 |
| Package_Shape | Square |
| Package_Style | GRID ARRAY |
| Programmable_Logic_Type | LOADABLE PLD |
| Propagation_Delay | 2.500 |
| Seated_Height_Max | 2.1000 |
| Supply_Voltage_Max | 2.62500 |
| Supply_Voltage_Min | 2.37500 |
| Supply_Voltage_Nom | 2.5 |
| Surface_Mount | Yes |
| Terminal_Form | Ball |
| Terminal_Pitch | 1.000 |
| Terminal_Position | Bottom |
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