EP20K400FC672-2V
Loadable PLD, 3.1ns, CMOS, PBGA672Manufacturer: Altera
Categories: Programmable Logic Devices
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Altera EP20K400 is a loadable PLD featuring 502 I/O lines and 4 dedicated inputs within a 672-ball PBGA package. This CMOS device offers a propagation delay of 3.1 ns and a maximum clock frequency of 34 MHz. The EP20K400 operates with a supply voltage range of 2.375V to 2.625V and has an operating temperature range of 0°C to 85°C. Its organization includes 496 outputs and 496 inputs, with macrocell output functions. This component is commonly found in telecommunications, industrial control, and computational systems. The device is surface-mount and comes in a square grid array package with a terminal pitch of 1.000 mm.
Additional Information
Series: EP20K400RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 27.0000 |
| Width | 27.0000 |
| Technology | CMOS |
| Clock_Frequency_Max | 34.00000 |
| JESD_30_Code | S-PBGA-B672 |
| Number_of_Dedicated_Inputs | 4 |
| Number_of_I_O_Lines | 502 |
| Number_of_Inputs | 496 |
| Number_of_Outputs | 496 |
| Number_of_Terminals | 672 |
| Operating_Temperature_Max | 85.0 |
| Operating_Temperature_Min | 0.0 |
| Organization | 4 DEDICATED INPUTS, 502 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | PLASTIC/EPOXY |
| Package_Code | BGA |
| Package_Equivalence_Code | BGA672,26X26,40 |
| Package_Shape | Square |
| Package_Style | GRID ARRAY |
| Programmable_Logic_Type | LOADABLE PLD |
| Propagation_Delay | 3.100 |
| Seated_Height_Max | 3.5000 |
| Supply_Voltage_Max | 2.62500 |
| Supply_Voltage_Min | 2.37500 |
| Supply_Voltage_Nom | 2.5 |
| Surface_Mount | Yes |
| Terminal_Form | Ball |
| Terminal_Pitch | 1.000 |
| Terminal_Position | Bottom |
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