EP20K200EBI356-2X
Loadable PLD, 1.97ns, CMOS, PBGA356Manufacturer: Altera
Categories: Programmable Logic Devices
Quality Control: Learn More
Altera EP20K200EBI356-2X is a loadable Programmable Logic Device (PLD) from the EP20K200 series, featuring CMOS technology and a 356-ball Grid Array package (PBGA356). This device offers 271 I/O lines and 4 dedicated inputs, with a macrocell output function. It operates with a minimum supply voltage of 1.71V and a maximum of 1.89V, nominal at 1.8V. The propagation delay is specified at 1.97ns, and the maximum clock frequency is 160MHz. This component is designed for surface mounting and operates within a temperature range of -40°C to 100°C. Applications for this device are found in telecommunications, industrial automation, and consumer electronics.
Additional Information
Series: EP20K200RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Width | 35.0000 |
| Technology | CMOS |
| Length | 35.0000 |
| Clock_Frequency_Max | 160.00000 |
| JESD_30_Code | S-PBGA-B356 |
| Number_of_Dedicated_Inputs | 4 |
| Number_of_I_O_Lines | 271 |
| Number_of_Inputs | 263 |
| Number_of_Outputs | 263 |
| Number_of_Terminals | 356 |
| Operating_Temperature_Max | 100.0 |
| Operating_Temperature_Min | -40.0 |
| Organization | 4 DEDICATED INPUTS, 271 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | PLASTIC/EPOXY |
| Package_Code | LBGA |
| Package_Equivalence_Code | BGA356,26X26,50 |
| Package_Shape | Square |
| Package_Style | GRID ARRAY, LOW PROFILE |
| Programmable_Logic_Type | LOADABLE PLD |
| Propagation_Delay | 1.970 |
| Seated_Height_Max | 1.6300 |
| Supply_Voltage_Max | 1.89000 |
| Supply_Voltage_Min | 1.71000 |
| Supply_Voltage_Nom | 1.8 |
| Surface_Mount | Yes |
| Terminal_Form | Ball |
| Terminal_Pitch | 1.270 |
| Terminal_Position | Bottom |
Request a Quote
Clients Also Buy
EP20K200RI208-2V
Loadable PLD, 3ns, CMOS, PQFP208
EP20K200QI240-1V
Loadable PLD, 2.5ns, CMOS, PQFP240
EP20K200RI208-3V
Loadable PLD, 3.6ns, CMOS, PQFP208