EP1830GC-20
OT PLD, 22ns, 48-Cell, CMOS, CPGA68Manufacturer: Altera
Categories: Programmable Logic Devices
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Altera EP1830 series OT PLD, part number EP1830GC-20, features a 48-macrocell organization within a CMOS technology. This device offers 12 dedicated inputs and 48 I/O lines, with a maximum clock frequency of 50 MHz. The propagation delay is rated at 22 ns. It operates within a supply voltage range of 4.75V to 5.25V and has an operating temperature range of 0°C to 70°C. The component is housed in a 68-pin ceramic PGA package (JESD-30 code S-XPGA-P68) with a 2.54 mm terminal pitch. Applications for this device are found in various industrial and consumer electronics sectors.
Additional Information
Series: EP1830RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 27.9400 |
| Width | 27.9400 |
| Technology | CMOS |
| Additional_Feature | No |
| Clock_Frequency_Max | 50.00000 |
| In_System_Programmable | No |
| JESD_30_Code | S-XPGA-P68 |
| JTAG_BST | No |
| Number_of_Dedicated_Inputs | 12 |
| Number_of_I_O_Lines | 48 |
| Number_of_Inputs | 64 |
| Number_of_Macro_Cells | 48 |
| Number_of_Outputs | 48 |
| Number_of_Terminals | 68 |
| Operating_Temperature_Max | 70.0 |
| Operating_Temperature_Min | 0.0 |
| Organization | 12 DEDICATED INPUTS, 48 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | Ceramic |
| Package_Code | PGA |
| Package_Equivalence_Code | PGA68,11X11 |
| Package_Shape | Square |
| Package_Style | GRID ARRAY |
| Programmable_Logic_Type | OT PLD |
| Propagation_Delay | 22.000 |
| Seated_Height_Max | 5.0038 |
| Supply_Voltage_Max | 5.25000 |
| Supply_Voltage_Min | 4.75000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | No |
| Terminal_Form | PIN/PEG |
| Terminal_Pitch | 2.540 |
| Terminal_Position | Perpendicular |
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