EP1810LI-25T
OT PLD, 28ns, CMOS, PQCC68Manufacturer: Altera
Categories: Programmable Logic Devices
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The Altera EP1810 is an OT PLD belonging to the EP1810 series. This CMOS device features 48 macrocells interconnected by global and/or local buses, supporting 4 external clocks. It offers 12 dedicated inputs and 48 I/O lines within a 68-terminal PQCC package (JESD-30 code S-PQCC-J68). With a maximum clock frequency of 40MHz and a propagation delay of 28ns, the EP1810 operates from a 4.5V to 5.5V supply. Its applications span industrial control, telecommunications, and consumer electronics. The component is surface-mount with a terminal pitch of 1.27mm and a square chip carrier package style. It is rated for an operating temperature range of -40°C to 85°C.
Additional Information
Series: EP1810RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Width | 24.2300 |
| Technology | CMOS |
| Length | 24.2300 |
| Additional_Feature | MACROCELLS INTERCONNECTED BY GLOBAL AND/OR LOCAL BUS; 48 MACROCELLS; 4 EXTERNAL CLOCKS |
| Clock_Frequency_Max | 40.00000 |
| JESD_30_Code | S-PQCC-J68 |
| Number_of_Dedicated_Inputs | 12 |
| Number_of_I_O_Lines | 48 |
| Number_of_Terminals | 68 |
| Operating_Temperature_Max | 85.0 |
| Operating_Temperature_Min | -40.0 |
| Organization | 12 DEDICATED INPUTS, 48 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | PLASTIC/EPOXY |
| Package_Code | QCCJ |
| Package_Equivalence_Code | LDCC68,1.0SQ |
| Package_Shape | Square |
| Package_Style | CHIP CARRIER |
| Programmable_Logic_Type | OT PLD |
| Propagation_Delay | 28.000 |
| Seated_Height_Max | 5.0800 |
| Supply_Voltage_Max | 5.50000 |
| Supply_Voltage_Min | 4.50000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | Yes |
| Terminal_Form | J BEND |
| Terminal_Pitch | 1.270 |
| Terminal_Position | QUAD |
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