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EP1810LI-25

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EP1810LI-25

OT PLD, 28ns, 48-Cell, CMOS, PQCC68

Manufacturer: Altera

Categories: Programmable Logic Devices

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Altera EP1810LI-25 is a CMOS OT PLD from the EP1810 series, featuring 48 macrocells and a propagation delay of 28ns. This device operates with a supply voltage range of 4.5V to 5.5V, with a nominal value of 5V, and supports a maximum clock frequency of 40MHz. It offers 48 I/O lines and 12 dedicated inputs, with macrocells interconnected via global and/or local buses. The component includes 4 external clocks. Packaged in a PQCC68 (JESD-30 code S-PQCC-J68) with a square chip carrier style and J-bend terminals on a 1.270mm pitch, it is designed for surface mounting. The operating temperature range is -40°C to +85°C. This PLD finds application in industrial automation, telecommunications, and consumer electronics.

Additional Information

Series: EP1810RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:
Technical Details:
TechnologyCMOS
Additional_FeatureMACROCELLS INTERCONNECTED BY GLOBAL AND/OR LOCAL BUS; 48 MACROCELLS; 4 EXTERNAL CLOCKS
Clock_Frequency_Max40.00000
In_System_ProgrammableNo
JESD_30_CodeS-PQCC-J68
JTAG_BSTNo
Number_of_Dedicated_Inputs12
Number_of_I_O_Lines48
Number_of_Macro_Cells48
Number_of_Terminals68
Operating_Temperature_Max85.0
Operating_Temperature_Min-40.0
Organization12 DEDICATED INPUTS, 48 I/O
Output_FunctionMACROCELL
Package_Body_MaterialPLASTIC/EPOXY
Package_CodeQCCJ
Package_Equivalence_CodeLDCC68,1.0SQ
Package_ShapeSquare
Package_StyleCHIP CARRIER
Programmable_Logic_TypeOT PLD
Propagation_Delay28.000
Supply_Voltage_Max5.50000
Supply_Voltage_Min4.50000
Supply_Voltage_Nom5
Surface_MountYes
Terminal_FormJ BEND
Terminal_Pitch1.270
Terminal_PositionQUAD

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