EP1810LC68-20T
OT PLD, 22ns, CMOS, PQCC68Manufacturer: Altera
Categories: Programmable Logic Devices
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The Altera EP1810LC68-20T is an Erasable Programmable Logic Device (EPLD) from the EP1810 series. This CMOS device features 48 Macrocells with shared input/clock functionality, organized with 12 dedicated inputs and 48 I/O lines. It offers a maximum clock frequency of 50 MHz and a typical propagation delay of 22 ns. Operating within a supply voltage range of 4.75V to 5.25V, this component is housed in a 68-terminal Plastic Quad Flat Pack (PQCC) package, specifically a J-leaded square chip carrier (JESD30 code S-PQCC-J68) with a terminal pitch of 1.270 mm. The operating temperature range is 0°C to 70°C. This device is well-suited for applications in industrial automation, telecommunications, and consumer electronics where flexible logic implementation is required.
Additional Information
Series: EP1810RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 24.2316 |
| Width | 24.2316 |
| Technology | CMOS |
| Additional_Feature | 48 MACROCELLS; SHARED INPUT/CLOCK |
| Clock_Frequency_Max | 50.00000 |
| JESD_30_Code | S-PQCC-J68 |
| Number_of_Dedicated_Inputs | 12 |
| Number_of_I_O_Lines | 48 |
| Number_of_Terminals | 68 |
| Operating_Temperature_Max | 70.0 |
| Operating_Temperature_Min | 0.0 |
| Organization | 12 DEDICATED INPUTS, 48 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | PLASTIC/EPOXY |
| Package_Code | QCCJ |
| Package_Equivalence_Code | LDCC68,1.0SQ |
| Package_Shape | Square |
| Package_Style | CHIP CARRIER |
| Programmable_Logic_Type | OT PLD |
| Propagation_Delay | 22.000 |
| Seated_Height_Max | 5.0800 |
| Supply_Voltage_Max | 5.25000 |
| Supply_Voltage_Min | 4.75000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | Yes |
| Terminal_Form | J BEND |
| Terminal_Pitch | 1.270 |
| Terminal_Position | QUAD |
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