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EP1810JI68-25

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EP1810JI68-25

UV PLD, 28ns, CMOS, CQCC68

Manufacturer: Altera

Categories: Programmable Logic Devices

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Altera EP1810 series UV PLD, part number EP1810JI68-25, offers a CMOS implementation with a 28ns propagation delay. This device features 48 macrocells with shared input/clock capabilities and 12 dedicated inputs, providing flexibility for complex logic designs. Operating within a temperature range of -40°C to 85°C, it supports a supply voltage from 4.5V to 5.5V. The component is housed in a 68-terminal CQCC package, identified by the S-CQCC-J68 code, measuring 24.13mm square with a metal-sealed cofired ceramic body and J-bend terminals on a 1.27mm pitch. This UV PLD is suitable for applications in industrial control, telecommunications, and data acquisition systems where robust, reprogrammable logic is required.

Additional Information

Series: EP1810RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:
Technical Details:
Length24.1300
Width24.1300
TechnologyCMOS
Additional_Feature48 MACROCELLS; SHARED INPUT/CLOCK
Clock_Frequency_Max40.00000
JESD_30_CodeS-CQCC-J68
Number_of_Dedicated_Inputs12
Number_of_I_O_Lines48
Number_of_Terminals68
Operating_Temperature_Max85.0
Operating_Temperature_Min-40.0
Organization12 DEDICATED INPUTS, 48 I/O
Output_FunctionMACROCELL
Package_Body_MaterialCERAMIC, METAL-SEALED COFIRED
Package_CodeWQCCJ
Package_Equivalence_CodeLDCC68,1.0SQ
Package_ShapeSquare
Package_StyleCHIP CARRIER, WINDOW
Programmable_Logic_TypeUV PLD
Propagation_Delay28.000
Seated_Height_Max5.0800
Supply_Voltage_Max5.50000
Supply_Voltage_Min4.50000
Supply_Voltage_Nom5
Surface_MountYes
Terminal_FormJ BEND
Terminal_Pitch1.270
Terminal_PositionQUAD

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