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EP1810JC68-35

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EP1810JC68-35

UV PLD, 40ns, CMOS, CQCC68

Manufacturer: Altera

Categories: Programmable Logic Devices

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The Altera EP1810JC68-35 is a UV Programmable Logic Device (PLD) from the EP1810 series. Engineered with CMOS technology, this component features 48 macrocells and shared input/clock functionality. It offers 12 dedicated inputs and 48 I/O lines within a 68-terminal CQCC (Ceramic Quad Flat Pack) package, specifically a J-lead style with a terminal pitch of 1.27mm. This square, metal-sealed, cofired ceramic package has a body length and width of 24.13mm and a seated height of 5.08mm. The device operates within a supply voltage range of 4.75V to 5.25V and has a maximum clock frequency of 28.60000 MHz. Its propagation delay is rated at 40ns. The operating temperature range is 0°C to 70°C. This component finds application in various industrial sectors requiring flexible logic implementation.

Additional Information

Series: EP1810RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:
Technical Details:
Width24.1300
TechnologyCMOS
Length24.1300
Additional_Feature48 MACROCELLS; SHARED INPUT/CLOCK
Clock_Frequency_Max28.60000
JESD_30_CodeS-CQCC-J68
Number_of_Dedicated_Inputs12
Number_of_I_O_Lines48
Number_of_Terminals68
Operating_Temperature_Max70.0
Operating_Temperature_Min0.0
Organization12 DEDICATED INPUTS, 48 I/O
Output_FunctionMACROCELL
Package_Body_MaterialCERAMIC, METAL-SEALED COFIRED
Package_CodeWQCCJ
Package_Equivalence_CodeLDCC68,1.0SQ
Package_ShapeSquare
Package_StyleCHIP CARRIER, WINDOW
Programmable_Logic_TypeUV PLD
Propagation_Delay40.000
Seated_Height_Max5.0800
Supply_Voltage_Max5.25000
Supply_Voltage_Min4.75000
Supply_Voltage_Nom5
Surface_MountYes
Terminal_FormJ BEND
Terminal_Pitch1.270
Terminal_PositionQUAD

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