EP1810JC-55
OT PLD, 55ns, 48-Cell, CMOS, CQCC68Manufacturer: Altera
Categories: Programmable Logic Devices
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The Altera EP1810JC-55 is an OT PLD from the EP1810 series, featuring a 55ns propagation delay and a 48-macrocell architecture. This CMOS device operates with a supply voltage ranging from 4.75V to 5.25V and is housed in a 68-terminal ceramic CQCC package (JESD-30 code S-XQCC-J68). It offers 12 dedicated inputs and 48 I/O lines, supporting a total of 60 inputs. The component is designed for surface mounting with a terminal pitch of 1.27mm. Its operating temperature range is 0°C to 70°C. This device finds application in various industrial and consumer electronics, including telecommunications and computing systems.
Additional Information
Series: EP1810RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 24.1300 |
| Width | 24.1300 |
| Technology | CMOS |
| Additional_Feature | No |
| In_System_Programmable | No |
| JESD_30_Code | S-XQCC-J68 |
| JTAG_BST | No |
| Number_of_Dedicated_Inputs | 12 |
| Number_of_I_O_Lines | 48 |
| Number_of_Inputs | 60 |
| Number_of_Macro_Cells | 48 |
| Number_of_Outputs | 48 |
| Number_of_Terminals | 68 |
| Operating_Temperature_Max | 70.0 |
| Operating_Temperature_Min | 0.0 |
| Organization | 12 DEDICATED INPUTS, 48 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | Ceramic |
| Package_Code | QCCJ |
| Package_Equivalence_Code | LDCC68,1.0SQ |
| Package_Shape | Square |
| Package_Style | CHIP CARRIER |
| Programmable_Logic_Type | OT PLD |
| Propagation_Delay | 55.000 |
| Seated_Height_Max | 5.0800 |
| Supply_Voltage_Max | 5.25000 |
| Supply_Voltage_Min | 4.75000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | Yes |
| Terminal_Form | J BEND |
| Terminal_Pitch | 1.270 |
| Terminal_Position | QUAD |
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