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EP1810JC-35

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EP1810JC-35

UV PLD, 40ns, 48-Cell, CMOS, CQCC68

Manufacturer: Altera

Categories: Programmable Logic Devices

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The Altera EP1810JC-35 is a UV Programmable Logic Device (PLD) from the EP1810 series, featuring 48 macrocells interconnected via global and/or local buses. This CMOS device operates with a maximum clock frequency of 28.60000 MHz and offers a propagation delay of 40.000 ns. It provides 12 dedicated inputs and 48 I/O lines, with a total of 60 inputs. The EP1810JC-35 is housed in a 68-terminal CQCC package (JESD-30 Code S-CQCC-J68) with a ceramic, metal-sealed cofired body. Operating within a temperature range of 0.0°C to 70.0°C, it requires a supply voltage between 4.75V and 5.25V. This component is suitable for applications in industrial and telecommunications sectors.

Additional Information

Series: EP1810RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:
Download Free CAD Model:Link image
Technical Details:
Width24.1300
TechnologyCMOS
Length24.1300
Additional_FeatureMACROCELLS INTERCONNECTED BY GLOBAL AND/OR LOCAL BUS; 48 MACROCELLS; 4 EXTERNAL CLOCKS
Clock_Frequency_Max28.60000
In_System_ProgrammableNo
JESD_30_CodeS-CQCC-J68
JTAG_BSTNo
Number_of_Dedicated_Inputs12
Number_of_I_O_Lines48
Number_of_Inputs60
Number_of_Macro_Cells48
Number_of_Outputs48
Number_of_Terminals68
Operating_Temperature_Max70.0
Operating_Temperature_Min0.0
Organization12 DEDICATED INPUTS, 48 I/O
Output_FunctionMACROCELL
Package_Body_MaterialCERAMIC, METAL-SEALED COFIRED
Package_CodeWQCCJ
Package_Equivalence_CodeLDCC68,1.0SQ
Package_ShapeSquare
Package_StyleCHIP CARRIER, WINDOW
Programmable_Logic_TypeUV PLD
Propagation_Delay40.000
Seated_Height_Max5.0800
Supply_Voltage_Max5.25000
Supply_Voltage_Min4.75000
Supply_Voltage_Nom5
Surface_MountYes
Terminal_FormJ BEND
Terminal_Pitch1.270
Terminal_PositionQUAD

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