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EP1810GM883B68-45

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EP1810GM883B68-45

UV PLD, 55ns, CMOS, CPGA68

Manufacturer: Altera

Categories: Programmable Logic Devices

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The Altera EP1810GM883B68-45 is a UV Programmable Logic Device (PLD) from the EP1810 series. This CMOS component features 48 macrocells with shared input/clock functionality and 12 dedicated inputs. It offers 48 I/O lines and operates within a supply voltage range of 4.5V to 5.5V, with a nominal voltage of 5V. The maximum clock frequency is 22.20000 MHz, and the typical propagation delay is 55ns. This device is housed in a 68-terminal ceramic, metal-sealed cofired square grid array package (CPGA68, S-CPGA-P68) with perpendicular pin/peg terminals on a 2.54mm pitch. It operates across an extended temperature range of -55°C to 125°C. Applications include aerospace and defense systems.

Additional Information

Series: EP1810RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:
Technical Details:
Width27.9400
TechnologyCMOS
Length27.9400
Additional_Feature48 MACROCELLS; SHARED INPUT/CLOCK
Clock_Frequency_Max22.20000
JESD_30_CodeS-CPGA-P68
Number_of_Dedicated_Inputs12
Number_of_I_O_Lines48
Number_of_Terminals68
Operating_Temperature_Max125.0
Operating_Temperature_Min-55.0
Organization12 DEDICATED INPUTS, 48 I/O
Output_FunctionMACROCELL
Package_Body_MaterialCERAMIC, METAL-SEALED COFIRED
Package_CodeWPGA
Package_ShapeSquare
Package_StyleGRID ARRAY, WINDOW
Programmable_Logic_TypeUV PLD
Propagation_Delay55.000
Seated_Height_Max4.9530
Supply_Voltage_Max5.50000
Supply_Voltage_Min4.50000
Supply_Voltage_Nom5
Surface_MountNo
Terminal_FormPIN/PEG
Terminal_Pitch2.540
Terminal_PositionPerpendicular

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