EP1810GM68-45
UV PLD, 50ns, CMOS, CPGA68Manufacturer: Altera
Categories: Programmable Logic Devices
Quality Control: Learn More
Altera's EP1810GM68-45 is a UV Programmable Logic Device (PLD) from the EP1810 series. This CMOS technology component features 48 macrocells and shared input/clock functionality, with 12 dedicated inputs and 48 I/O lines. It operates with a maximum clock frequency of 22.20000 MHz and a propagation delay of 50.000 ns. The device is housed in a 68-terminal ceramic, metal-sealed cofired square grid array package (CPGA68, S-CPGA-P68) with a terminal pitch of 2.54 mm. It supports a supply voltage range of 4.5V to 5.5V. This component is suitable for applications in industrial and telecommunications sectors.
Additional Information
Series: EP1810RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Width | 27.9400 |
| Technology | CMOS |
| Length | 27.9400 |
| Additional_Feature | 48 MACROCELLS; SHARED INPUT/CLOCK |
| Clock_Frequency_Max | 22.20000 |
| JESD_30_Code | S-CPGA-P68 |
| Number_of_Dedicated_Inputs | 12 |
| Number_of_I_O_Lines | 48 |
| Number_of_Terminals | 68 |
| Operating_Temperature_Max | 125.0 |
| Operating_Temperature_Min | -55.0 |
| Organization | 12 DEDICATED INPUTS, 48 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | CERAMIC, METAL-SEALED COFIRED |
| Package_Code | WPGA |
| Package_Shape | Square |
| Package_Style | GRID ARRAY, WINDOW |
| Programmable_Logic_Type | UV PLD |
| Propagation_Delay | 50.000 |
| Seated_Height_Max | 4.9530 |
| Supply_Voltage_Max | 5.50000 |
| Supply_Voltage_Min | 4.50000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | No |
| Terminal_Form | PIN/PEG |
| Terminal_Pitch | 2.540 |
| Terminal_Position | Perpendicular |
Request a Quote
Clients Also Buy
EP1810GM883B
OT PLD, 50ns, 48-Cell, CMOS, CPGA68
EP1810JI-40
OT PLD, 45ns, 48-Cell, CMOS, CQCC68
EP1810JM68-45
UV PLD, 50ns, CMOS, CQCC68