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EP1810GM-45/883

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EP1810GM-45/883

UV PLD, 55ns, CMOS, CPGA68

Manufacturer: Altera

Categories: Programmable Logic Devices

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The Altera EP1810GM-45-883 is a CMOS UV Programmable Logic Device from the EP1810 series, featuring 48 macrocells interconnected by global and local buses. This component offers 12 dedicated inputs and 48 I/O lines, supporting up to 4 external clocks. With a maximum clock frequency of 22.2 MHz and a propagation delay of 55 ns, it operates within a temperature range of -55°C to 125°C. The device is housed in a 68-terminal Ceramic Pin Grid Array (CPGA) package (JESD-30 Code: S-CPGA-P68) with a terminal pitch of 2.54 mm. It requires a supply voltage between 4.5V and 5.5V. This component is suitable for demanding applications in aerospace and defense, as well as industrial control systems requiring radiation-hardened and high-reliability components.

Additional Information

Series: EP1810RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:
Download Free CAD Model:Link image
Technical Details:
Width27.9400
TechnologyCMOS
Length27.9400
Additional_FeatureMACROCELLS INTERCONNECTED BY GLOBAL AND/OR LOCAL BUS; 48 MACROCELLS; 4 EXTERNAL CLOCKS
Clock_Frequency_Max22.20000
JESD_30_CodeS-CPGA-P68
Number_of_Dedicated_Inputs12
Number_of_I_O_Lines48
Number_of_Terminals68
Operating_Temperature_Max125.0
Operating_Temperature_Min-55.0
Organization12 DEDICATED INPUTS, 48 I/O
Output_FunctionMACROCELL
Package_Body_MaterialCERAMIC, METAL-SEALED COFIRED
Package_CodeWPGA
Package_Equivalence_CodePGA68,11X11
Package_ShapeSquare
Package_StyleGRID ARRAY, WINDOW
Programmable_Logic_TypeUV PLD
Propagation_Delay55.000
Screening_Level_Reference_StandardMIL-STD-883
Seated_Height_Max4.9600
Supply_Voltage_Max5.50000
Supply_Voltage_Min4.50000
Supply_Voltage_Nom5
Surface_MountNo
Terminal_FormPIN/PEG
Terminal_Pitch2.540
Terminal_PositionPerpendicular

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