EP1810GI-40
OT PLD, 45ns, 48-Cell, CMOS, CPGA68Manufacturer: Altera
Categories: Programmable Logic Devices
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The Altera EP1810GI-40 is a CMOS OT PLD from the EP1810 series, featuring a 45ns propagation delay and 48 macrocells. This component is housed in a CPGA68 package, specified by JEDEC code S-XPGA-P68, with a square ceramic grid array body and perpendicular pin terminals on a 2.54mm pitch. It offers 48 I/O lines, 12 dedicated inputs, and a total of 60 input lines. Operating within a temperature range of -40°C to 85°C, it requires a supply voltage between 4.75V and 5.25V. This device is suitable for applications in industrial control, telecommunications, and consumer electronics requiring flexible logic implementation.
Additional Information
Series: EP1810RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Width | 27.9400 |
| Technology | CMOS |
| Length | 27.9400 |
| Additional_Feature | No |
| In_System_Programmable | No |
| JESD_30_Code | S-XPGA-P68 |
| JTAG_BST | No |
| Number_of_Dedicated_Inputs | 12 |
| Number_of_I_O_Lines | 48 |
| Number_of_Inputs | 60 |
| Number_of_Macro_Cells | 48 |
| Number_of_Outputs | 48 |
| Number_of_Terminals | 68 |
| Operating_Temperature_Max | 85.0 |
| Operating_Temperature_Min | -40.0 |
| Organization | 12 DEDICATED INPUTS, 48 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | Ceramic |
| Package_Code | PGA |
| Package_Equivalence_Code | PGA68,11X11 |
| Package_Shape | Square |
| Package_Style | GRID ARRAY |
| Programmable_Logic_Type | OT PLD |
| Propagation_Delay | 45.000 |
| Seated_Height_Max | 5.0038 |
| Supply_Voltage_Max | 5.25000 |
| Supply_Voltage_Min | 4.75000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | No |
| Terminal_Form | PIN/PEG |
| Terminal_Pitch | 2.540 |
| Terminal_Position | Perpendicular |