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EP1810GC68-35

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EP1810GC68-35

UV PLD, 40ns, 48-Cell, CMOS, CPGA68

Manufacturer: Altera

Categories: Programmable Logic Devices

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Altera EP1810GC68-35 is a CMOS UV Programmable Logic Device from the EP1810 series. This component features 48 macrocells with shared input/clock functionality and a maximum clock frequency of 40 MHz. It offers 12 dedicated inputs and 48 I/O lines, supporting a total of 60 inputs. The propagation delay is rated at 40 ns. This device operates within a supply voltage range of 4.75V to 5.25V, with a nominal voltage of 5V, and has an operating temperature range of 0°C to 70°C. It is housed in a 68-pin ceramic, metal-sealed cofired grid array package (CPGA68) with a square shape and window style, designed for through-hole mounting. This PLD finds application in various industrial and telecommunications systems.

Additional Information

Series: EP1810RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:
Download Free CAD Model:Link image
Technical Details:
Width27.9400
TechnologyCMOS
Length27.9400
Additional_Feature48 MACROCELLS; SHARED INPUT/CLOCK
Clock_Frequency_Max40.00000
In_System_ProgrammableNo
JESD_30_CodeS-CPGA-P68
JTAG_BSTNo
Number_of_Dedicated_Inputs12
Number_of_I_O_Lines48
Number_of_Inputs60
Number_of_Macro_Cells48
Number_of_Outputs48
Number_of_Terminals68
Operating_Temperature_Max70.0
Operating_Temperature_Min0.0
Organization12 DEDICATED INPUTS, 48 I/O
Output_FunctionMACROCELL
Package_Body_MaterialCERAMIC, METAL-SEALED COFIRED
Package_CodeWPGA
Package_Equivalence_CodePGA68,11X11
Package_ShapeSquare
Package_StyleGRID ARRAY, WINDOW
Programmable_Logic_TypeUV PLD
Propagation_Delay40.000
Seated_Height_Max4.9600
Supply_Voltage_Max5.25000
Supply_Voltage_Min4.75000
Supply_Voltage_Nom5
Surface_MountNo
Terminal_FormPIN/PEG
Terminal_Pitch2.540
Terminal_PositionPerpendicular

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