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EP1810GC-45

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EP1810GC-45

UV PLD, 50ns, 48-Cell, CMOS, CPGA68

Manufacturer: Altera

Categories: Programmable Logic Devices

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Altera EP1810GC-45 is a UV Programmable Logic Device (PLD) from the EP1810 series, featuring 48 macrocells interconnected by global and/or local buses. This CMOS device offers 12 dedicated inputs and supports up to 48 I/O lines, with 4 external clock inputs. The propagation delay is 50ns, and the maximum clock frequency is 22.2 MHz. It operates with a supply voltage range of 4.75V to 5.25V and has a temperature range of 0°C to 70°C. The component is housed in a 68-pin Ceramic Pin Grid Array (CPGA) package with a JEDEC standard S-CPGA-P68 code. This device finds application in high-reliability systems within industrial and military sectors.

Additional Information

Series: EP1810RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:
Download Free CAD Model:Link image
Technical Details:
Width27.9400
TechnologyCMOS
Length27.9400
Additional_FeatureMACROCELLS INTERCONNECTED BY GLOBAL AND/OR LOCAL BUS; 48 MACROCELLS; 4 EXTERNAL CLOCKS
Clock_Frequency_Max22.20000
In_System_ProgrammableNo
JESD_30_CodeS-CPGA-P68
JTAG_BSTNo
Number_of_Dedicated_Inputs12
Number_of_I_O_Lines48
Number_of_Inputs60
Number_of_Macro_Cells48
Number_of_Outputs48
Number_of_Terminals68
Operating_Temperature_Max70.0
Operating_Temperature_Min0.0
Organization12 DEDICATED INPUTS, 48 I/O
Output_FunctionMACROCELL
Package_Body_MaterialCERAMIC, METAL-SEALED COFIRED
Package_CodePGA
Package_Equivalence_CodePGA68,11X11
Package_ShapeSquare
Package_StyleGRID ARRAY
Programmable_Logic_TypeUV PLD
Propagation_Delay50.000
Seated_Height_Max4.9600
Supply_Voltage_Max5.25000
Supply_Voltage_Min4.75000
Supply_Voltage_Nom5
Surface_MountNo
Terminal_FormPIN/PEG
Terminal_Pitch2.540
Terminal_PositionPerpendicular

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