EP1210PC-2
OT PLD, 65ns, PAL-Type, CMOS, PDIP40Manufacturer: Altera
Categories: Programmable Logic Devices
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Altera's EP1210PC-2 is a CMOS OT PLD from the EP1210 series, featuring a PAL-type architecture. This device offers 28 macrocells and 236 product terms, supporting up to 36 inputs and 24 I/O lines. With a maximum clock frequency of 23.2 MHz and a propagation delay of 65 ns, it is suitable for applications requiring flexible logic implementation. The EP1210PC-2 operates within a supply voltage range of 4.75V to 5.25V and a temperature range of 0°C to 70°C. It is housed in a 40-pin PDIP (R-PDIP-T40) through-hole package, with a terminal pitch of 2.54mm. This component finds application in industrial control, telecommunications, and consumer electronics.
Additional Information
Series: EP1210RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 52.3240 |
| Width | 15.2400 |
| Technology | CMOS |
| Architecture | PAL-TYPE |
| Additional_Feature | 28 MACROCELLS |
| Clock_Frequency_Max | 23.20000 |
| JESD_30_Code | R-PDIP-T40 |
| Number_of_Dedicated_Inputs | 12 |
| Number_of_I_O_Lines | 24 |
| Number_of_Inputs | 36 |
| Number_of_Outputs | 24 |
| Number_of_Product_Terms | 236 |
| Number_of_Terminals | 40 |
| Operating_Temperature_Max | 70.0 |
| Operating_Temperature_Min | 0.0 |
| Organization | 12 DEDICATED INPUTS, 24 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | PLASTIC/EPOXY |
| Package_Code | DIP |
| Package_Equivalence_Code | DIP40,.6 |
| Package_Shape | Rectangular |
| Package_Style | IN-LINE |
| Programmable_Logic_Type | OT PLD |
| Propagation_Delay | 65.000 |
| Seated_Height_Max | 4.8300 |
| Supply_Voltage_Max | 5.25000 |
| Supply_Voltage_Min | 4.75000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | No |
| Terminal_Form | THROUGH-HOLE |
| Terminal_Pitch | 2.540 |
| Terminal_Position | Dual |
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