5962-9473301MXX
Loadable PLD, CMOS, CPGA232Manufacturer: Altera
Categories: Programmable Logic Devices
Quality Control: Learn More
Altera 5962-9473301MXX is a loadable PLD from the 5962-9473301 series. This CMOS component features 1188 flip-flops and 1008 logic elements, offering configurable I/O operation supporting 3.3V or 5V. It is housed in a 232-pin ceramic, metal-sealed cofired ceramic pin grid array (CPGA232) package with a terminal pitch of 2.540 mm. The device provides 4 dedicated inputs and 180 I/O lines with registered output functions. Operating across a temperature range of -55°C to +125°C, it requires a supply voltage between 4.5V and 5.5V, nominal at 5V. This MIL-STD-883 screened component is utilized in demanding applications across aerospace, defense, and industrial sectors.
Additional Information
Series: 5962-9473301RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 44.7000 |
| Width | 44.7000 |
| Technology | CMOS |
| Additional_Feature | 1188 FLIP FLOPS; 1008 LOGIC ELEMENTS; CONFIGURABLE I/O OPERATION (3.3V OR 5V) |
| JESD_30_Code | S-CPGA-P232 |
| Number_of_Dedicated_Inputs | 4 |
| Number_of_I_O_Lines | 180 |
| Number_of_Terminals | 232 |
| Operating_Temperature_Max | 125.0 |
| Operating_Temperature_Min | -55.0 |
| Organization | 4 DEDICATED INPUTS, 180 I/O |
| Output_Function | REGISTERED |
| Package_Body_Material | CERAMIC, METAL-SEALED COFIRED |
| Package_Code | PGA |
| Package_Shape | Square |
| Package_Style | GRID ARRAY |
| Programmable_Logic_Type | LOADABLE PLD |
| Screening_Level_Reference_Standard | MIL-STD-883 |
| Seated_Height_Max | 5.2070 |
| Supply_Voltage_Max | 5.50000 |
| Supply_Voltage_Min | 4.50000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | No |
| Terminal_Form | PIN/PEG |
| Terminal_Pitch | 2.540 |
| Terminal_Position | Perpendicular |
Request a Quote
Clients Also Buy
5962-9473301MXC
Loadable PLD, CMOS, CPGA232
EPM5128GI
UV PLD, 55ns, 128-Cell, CMOS, CPGA68
EPF10K100EFC672-1X
Loadable PLD, 9ns, CMOS, PBGA672