·      What Zephyr RTOS is

·      Why AMD is adopting Zephyr

·      Zephyr RTOS vs FreeRTOS

·      MicroBlaze™ V RISC-V ISA support

·      AMD’s Zephyr roadmap (EA and PROD phases)

·      AXI driver availability

·      FPGA integration details

Devicetree-based architecture: Makes supporting new boards quick and straightforward

Rich built-in networking support including:

·      IPv6

·      IPv4

·      UDP

·      TCP

·      ICMPv4

·      ICMPv6

·      Clones and manages repositories (modules) “under the hood” of a Zephyr project

·      Builds Zephyr applications

·      Flashes boards

·      Helps debug Zephyr applications

·      Can be extended with custom Python-based commands

·      west.yml

·      Modules

·      Zephyr code base

·      Applications integrating via Kconfig and prj.conf

·      <board>.dts device tree files

west.yml → Modules → Zephyr code base → Applications

·      Turn features on or off

·      Configure networking

·      Configure debugging

·      Select scheduler algorithms

·      Enable other Zephyr kernel capabilities

·      Kconfig

·      prj.conf

·      R52 on a VCK190

·      AMD MicroBlaze™ V on a KCU105

·      Other boards/devices

·      A rich ecosystem of devices and features

·      Strong community support backed by the Linux Foundation

·      Devicetree architecture

·      Hardware Abstraction Layer (HAL)

·      Built-in POSIX compliance

·      Additional features beyond those listed

·      Integrated into your build system

·      Configured via FreeRTOSConfig.h

·      west (meta-tool)

·      CMake + Ninja

·      Kconfig for feature configuration

·      Devicetree for hardware description

·      No enforced driver model

·      Vendor SDKs provide drivers

·      Consistent driver/device model

·      Improved portability across boards

·      Networking optional (FreeRTOS+TCP or vendor stacks)

·      IP networking

·      BLE

·      Mesh

·      Sockets APIs

·      TLS options

·      Integrated workflow

·      Tiny MCU app

·      Minimal overhead

·      Vendor SDK environment

·      Simple scheduler needs

·      Connected device (BLE/Wi-Fi/IP)

·      Multiple boards/products

·      Long-lived codebase

·      Upstream driver support

·      Standardized configuration

·      Booting initial shell/application

·      Interrupt handling

·      Exceptions

·      Memory management

·      Bus interfaces

·      Single/double precision floating point

·      Extensive testing

·      Regression testing and validation

·      Additional features are added

·      Kernel updates are performed

·      FreeRTOS maintenance

·      Zephyr PROD (2025.1)

·      FreeRTOS Maintenance

·      Zephyr EA (2026.2)

·      Zephyr EA (2026.1)

·      Zephyr PROD (2026.2)

·      Zephyr EA (2025.2)

·      Zephyr PROD (2026.1)

·      Zephyr SMP Support (2026.1)

·      Zephyr EA (2026.1)

·      Zephyr PROD (2026.2)

·      Zephyr EA (2025.1)

·      Zephyr MPU Support (2025.2)

·      Zephyr PROD (2025.2)

·      Registers

·      Instruction set

·      Programmer’s model

·      Base instruction sets (rv32i, rv64i)

·      Extensions (m, a, f, c, etc.)

·      Works with AMD FPGAs

·      Works with AMD Zynq™ families

·      Works with AMD Versal™ adaptive SoCs

·      Supported in Vivado™ ML Design Suite

·      Highly configurable footprint

·      Up to 3.52 CoreMark/MHz

·      Wide range of optimized Ips

·      Deployable in programmable logic (PL)

·      WFI instructions for low power

·      Plug-and-Play

·      Compatible with classic MicroBlaze

·      Three preset configurations

·      Highly scalable

·      rv32i

·      rv64i

·      m (integer multiply/divide)

·      a (atomic instructions)

·      f (single-precision floating point, rv32i only, requires m)

·      fd (double-precision floating point, rv64i only, requires m)

·      c (compressed instructions)

·      b, Zb[abcs] (bit manipulation extensions)

·      Zicsr (CSR extension)

·      Zifencei (instruction-fetch fence)

·      Zicbom (cache block management)

·      Add 16-bit instruction encodings

·      Reduce code size

·      50 - 60% of instructions typically replaced

·      25 - 30% total code-size reduction

·      Memory savings

·      Improved cache performance

·      May reduce maximum clock rate

·      2026.1+: Support further optional –Zc compression

·      RISC-V Instruction Set Manual Volume I: User-Level ISA v1.7

·      Timer

·      Uartlite

·      Interrupt controller

·      GPIO

·      SPI

·      I2C

·      16550 UART

·      AXI stream works well; no driver required

·      Ethernet support coming soon

·      Zephyr CONFIG_XIP allows code/data split

·      Many applications fit easily in BRAM

·      A shift toward a scalable RTOS platform

·      Strong RISC-V ecosystem alignment

·      Production-ready AXI drivers

·      Clear EA → PROD roadmap

·      FPGA-native embedded integration

The AMD MicroBlaze V processor is highly configurable, consistent with its RISC-V-based architecture and soft-processor implementation within AMD FPGAs. Designers can select supported ISA extensions (e.g., M, A, F, D, C, bit manipulation extensions, CSR, etc.) and determine whether certain operations are implemented in hardware (for performance) or emulated in software (to reduce resource utilization).

Because MicroBlaze V is implemented as a soft processor in programmable logic, system architects can instantiate multiple independent processor cores within the FPGA fabric if required by the application.

Zephyr RTOS uses Devicetree to describe hardware configuration. During the build process, Zephyr reads the hardware description (generated via XSA → SDTGen → west lopper-command) and integrates it into the system’s Devicetree configuration. If a multi-core configuration is instantiated and properly described in the hardware design, Zephyr detects the hardware layout through this Devicetree-based configuration mechanism.

No. While AMD provides preset configurations to accelerate development and improve design productivity, MicroBlaze V is highly configurable and can be tailored to meet specific application requirements.

Preset configurations are provided for convenience and faster time-to-design, but custom configurations are fully supported.

Zephyr RTOS is supported on devices that are supported by AMD Vivado ML Design Suite and can accommodate a MicroBlaze V processor instance.

Because MicroBlaze V is implemented in programmable logic, Zephyr can run on any AMD FPGA device (including AMD FPGAs, Zynq families, and Versal adaptive SoCs) that:

·      Is supported by Vivado

·      Has sufficient programmable logic and memory resources to instantiate the MicroBlaze™ V processor and required peripherals

No. The majority of drivers required for MicroBlaze V support have reached production quality status.

Production-quality drivers include:

·      Timer

·      Uartlite

·      Interrupt controller

·      GPIO

·      SPI

·      I2C

·      16550 UART

A small number of features are still being finalized and refined toward full production quality. AXI Stream functionality works without requiring a dedicated driver, and Ethernet support is forthcoming.

Any MicroBlaze V configuration can support Zephyr RTOS, provided that a timer peripheral is available.

A timer is required to support the RTOS scheduling and timekeeping functionality. As long as the processor configuration includes a timer and sufficient system resources, Zephyr can be deployed.

It is recommended to use the latest version of Vivado ML Design Suite.

For best compatibility, the Vivado version should align with the Zephyr version being used in the project. Matching toolchain and RTOS versions ensures consistent hardware description generation and integration.

No. Zephyr RTOS is not included in the Vivado installation.

Zephyr is an open-source RTOS hosted by the Linux Foundation and must be installed separately. Integration with Vivado-based hardware designs is performed using the Zephyr build system, West meta-tool, and the AMD-specific lopper-command flow.

The transition from FreeRTOS to Zephyr is driven by several strategic and technical considerations:

·      Strong and growing community momentum behind Zephyr

·      Backing by the Linux Foundation

·      Rich ecosystem of devices and features

·      Devicetree-based hardware abstraction

·      Built-in POSIX compliance

·      Improved portability across architectures

·      Reduced long-term maintenance burden

Zephyr’s broader ecosystem support and long-term sustainability make it a more scalable and future-ready platform for AMD processor roadmaps.